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IA^3 - WORKSHOP ON IRREGULAR APPLICATIONS: ARCHITECTURES & ALGORITHMS
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http://cass-mt.pnnl.gov/irregularworkshop.aspx

November 13, 2011
Seattle, WA, USA

To be held in conjunction with:
SC11 (http://sc11.supercomputing.org/)

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THEME
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Many data intensive scientific applications are irregular by nature. They may present irregular data structures, control flow or communication. Current supercomputing systems are organized around components optimized for data locality and regular computation. Developing irregular applications on them demands a substantial effort, and often leads to poor performance. However, solving these applications efficiently will be a key requirement for future systems.

The solutions needed to address their challenges can only come by considering the problem from all the points of view, from micro to system-architectures, from compilers to languages, from libraries to runtimes, up to rethinking how algorithms operate. Only collaborative efforts among researchers with different profiles, including end users, domain experts, and computer scientists, could lead to significant breakthroughs. This workshop aims at bringing together scientists with all these different backgrounds to discuss, define and design methods and technologies for efficiently supporting irregular applications on current and future machines.

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CALL FOR PAPERS
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Irregular applications are a broad class of applications with unpredictable memory access patterns, control structures, and/or network transfers. They typically use pointer-based data structures such as graphs and trees, often present fine-grained synchronization and communication, and generally operate on very large data sets. They have a significant degree of latent parallelism, which however is difficult to exploit due to their complex behavior. Current high performance architectures rely on data locality and regular computation to tolerate access latencies, and often do not cope well with the requirements of these applications. Furthermore, irregular applications are difficult to scale on current supercomputing machines, due to their limits in fine-grained synchronization and small data transfers.

Irregular applications pertain both to well established and emerging fields, such as Computer Aided Design (CAD), bioinformatics, semantic graph databases, social network analysis, security. Addressing the issues of these applications on current and future architectures will become critical to solve the scientific challenges of the next few years. This workshop seeks to explore solutions for supporting efficient execution of irregular applications in the form of new features at the level of the micro- and system-architecture, network, languages and libraries, runtimes, compilers, analysis, algorithms. Topics of interest, of both theoretical and practical significance, include but are not limited to:

- Micro- and System-architectures
- Network and memory architectures
- Heterogeneous and custom architectures (GPUs, FPGAs)
- Modeling and evaluation of architectures
- Innovative algorithms
- Parallelization techniques and data structures
- Languages and programming models
- Library and runtime support
- Compiler and analysis techniques

Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged. We solicit both 8-page regular papers and 4-page position papers.

Authors of selected papers from the workshop will be invited to submit an extended version of their manuscript to the Special Issue on: "Architectures and Algorithms for Irregular Applications" of the International Journal of High Performance Computing and Networking (Inderscience publisher - http://www.inderscience.com/browse/callpaper.php?callID=1689).

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PAPER SUBMISSION GUIDELINES
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Authors should submit an abstract by Thursday, 15 September 2011 (11.59 PM PDT - EXTENDED). They should submit the full version of the paper by Thursday, 15 September 2011 (11.59 PM PDT - EXTENDED). All submissions should be in double-column, single-spaced letter format, using 10-point size fonts, with at least 1 inch margins on each side. Submitted manuscripts may not exceed 8 pages in length for regular papers and 4 pages for position papers including figures, tables and references.

To submit a paper, please go to EasyChair (http://www.easychair.org/conferences/?conf=ia3) and follow the instructions.

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IMPORTANT DATES
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15 September 2011 (11.59 PM PDT - EXTENDED): Abstract submission
15 September 2011 (11.59 PM PDT - EXTENDED): Full or position paper submission
10 October 2011: Notification of acceptance
24 October 2011: Camera-ready due
13 November 2011: Workshop

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ORGANIZERS
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John Feo (Pacific Northwest National Laboratory) - john.feo@pnnl.gov
Oreste Villa (Pacific Northwest National Laboratory) - oreste.villa@pnnl.gov
Antonino Tumeo (Pacific Northwest National Laboratory) - antonino.tumeo@pnnl.gov
Simone Secchi (Pacific Northwest National Laboratory) - simone.secchi@pnnl.gov

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PROGRAM COMMITTEE
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David A. Bader, Georgia Tech
Udeepta Bordoloi, AMD
Bryan Catanzaro, NVIDIA
Daniel Chavarria, Pacific Northwest National Laboratory
Roberto Gioiosa, Barcelona Supercomputing Center
Matteo Monchiero, Intel
Walid Najjar, University of California Riverside
Gianluca Palermo, Politecnico di Milano
Cristina Silvano, Politecnico di Milano
Pedro Trancoso, University of Cyprus