Recent years have seen a surge of machine learning contributions across the chip design stack, tackling one of the most complex and consequential challenges in computer science today. Despite this momentum, the machine learning and electronic design automation (EDA) communities remain largely disconnected.

This workshop brings both communities together at a pivotal moment, when semiconductor design sits at the center of global economic and strategic priorities, hardware designer shortages are acute, and AI-driven design tools are approaching production readiness.

We invite submissions describing novel research, applications, systems, datasets, and position papers at the intersection of machine learning and chip/electronic design automation.

Topics include, but are not limited to:

- Machine learning for physical design: placement, routing, and floorplanning
- ML for RTL, logic synthesis, and technology mapping
- Timing, power, and area prediction and optimization
- Graph neural networks for circuits and netlists
- Generative models (e.g., diffusion, flow matching) for layout and design
- Reinforcement learning for EDA tasks, including script generation, testbench production, and module completion
- Large language models and foundation models for hardware description languages (Verilog, VHDL, and SystemVerilog)
- Agentic systems for chip design workflows with tool use (linters, synthesizers, simulators, timing analyzers, etc.)
- Reproducible benchmarks, datasets, and open-source infrastructure
- Societal, educational, and workforce aspects of AI-driven chip design

We particularly encourage submissions that promote reproducibility through open-source code, datasets, model weights, evaluation frameworks, or other openly available research artifacts.