CALL FOR PAPERS

Network-on-Chips (NoCs) play a crucial role in determining the overall performance, energy usage, and reliability of many-core processing architectures. NoCs are part of an increasingly large number of products that we use every day – demonstrating that the NoC paradigm is practical, scalable, and can be adapted to support multiple computational paradigms, ranging from multiprocessing and reconfigurable computing to the emerging areas of AI and neuromorphic computing. The goal of the NoCArc Workshop is to provide a forum for researchers and practitioners to present and discuss innovative ideas and solutions related to the design, implementation, testing and application of NoCs and NoC based many-core architectures. Topics of specific interest for the workshop include, but are not limited to:

Machine Learning (ML) and NoC-based systems
* ML for modeling and prediction
* ML based algorithms, optimization, and design methodologies
* Novel interconnections for domain specific ML architectures
* Memory access for the NoC-based ML systems

NoC Architecture and Implementation
* Topologies, routing, and flow control
* Managing QoS
* Reliability and security issues
* Design methodologies and tools

NoC Analysis, Optimization, and Verification
* Power, energy, and thermal issues
* Benchmarking and experience with NoC-based systems
* Modeling, simulation, and synthesis
* Debug, test and verification of NoCs and NoC-based systems

NoC Applications
* Mapping of applications onto NoCs
* Real and industrial NoC case studies
* NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
* NoC designs for heterogeneous systems

NoC at System-level
* NoC support for designing and accessing memory subsystems
* OS support for NoCs
* Existing and novel programming models including shared memory, message passing, etc
* Large-scale systems (datacenters and supercomputers) with NoC-based systems as building blocks

NoC at System-level
* NoC for quantum architectures
* Wireless, Optical, and RF
* NoCs for 3D and 2.5D packages including Network-in-Package (NiP)
* Approximate computing for NoCs and NoC-based systems
* Chip-to-Chip Interconnects

Besides regular papers, papers describing “work in progress” or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.

GENERAL CHAIR
* Poona Bahrebar, Ghent University, Belgium

PROGRAM CO-CHAIRS
* Abhijit Das, Universitat Politécnica de Catalunya, Spain
* Md Farhadur Reza, Eastern Illinois University, USA

PUBLICITY CHAIRS
* José L. Abellán, University of Murcia, Spain
* Alireza Monemi, Barcelona Supercomputing Center, Spain

STEERING COMMITTEE
* Maurizio Palesi, University of Catania, Italy
* Masoud Daneshtalab, Mälardalen University, Sweden
* Xiaohang Wang, Guangzhou Institute of Advanced Technology, China
* Davide Patti, University of Catania, Italy
* Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology, Sweden
* Kun-Chih (Jimmy) Chen, National Sun Yat-sen University, Taiwan
* Sergi Abadal, Universitat Politècnica de Catalunya, Spain
* Amlan Ganguly, Rochester Institute of Technology, NY, USA
* Salvatore Monteleone, Niccolò Cusano University, Italy
* Cristinel Ababei, Marquette University, USA

IMPORTANT DATES
* Abstract submission deadline: July 31, 2023 (extended)
* Full paper submission deadline: July 31, 2023 (extended)
* Author notification: August 15, 2023
* Camera-ready version due: September 1, 2023

NoCArc Workshop will be held on October 28/29, 2023 in conjunction with the 56th IEEE/ACM International Symposium on Microarchitecture® (MICRO-56)