Background and Focus:
Although the basic reliability of hardware and software components has improved
over decades, their increasing number causes severe problems. Moreover, in recent years it can be observed
that an increasing number of devices are integrated into environments of other physical components such
as automotive or digital systems. Here, the complexity and number of interactions with these components
creates problems with regard to maintaining a dependable operation of the entire system in case of faults
or external disturbances. While this is not a problem with microprocessors, shrinking feature sizes, higher
complexity, lower voltages, and higher clock frequencies increase the probability of design-, manufacturing-
, and operational faults, making fault tolerance techniques in general purpose processors to be of crucial
importance in the future. As simple solutions (such as TMR) can easily get too expensive, the ability to trade
increased reliability against performance/power overhead will become important, resulting in light-weight fault
tolerance techniques implemented in hardware, but controllable from higher software layers.
This workshop aims at presenting contributions and work-in-progress from the research area of depend-
able and fault-tolerant computing in order to bring together scientists working in related fields.
Topics Contributions on the topic of “Dependable Embedded Systems“ are of particular interest; contri-
butions on general topics of dependability and fault tolerance are also welcome but not limited to:
• dependable computer systems, networks and embedded systems
• modeling, simulation and evaluation of fault-tolerant systems
• dependability of mechatronic systems
• reliability models for hardware and software
• fault-tolerant systems and system components
• validation and verification
• safety-critical applications
• fault models and fault abstraction
• highly available systems
• real-time and performance guarantees
• testing of hardware and software
• fault detection and fault treatment
• failure prediction
• fault injection techniques
• on-chip fault-tolerance
• software-controlled fault tolerance
• fault-tolerant processor architecture
• fault-tolerance in operating systems, storage and database systems

The workshop will focus on research presentations as well as brainstorming sessions.
Therefore, two kinds of contributions are welcome:
• research papers documenting results of scientific investigations and
• position papers proposing strategies or discussing open problems.

Informations for Authors:
Accepted papers will be published by VDE and IEEExplore.
Papers should be in English and formatted according to IEEE eXpress ”co

Workshop Chairs:
Bernhard Fechner, University of Hagen, Germany
Peter Sobe, HTW Dresden, Germany
Karl-Erwin Großpietsch, St. Augustin, Germany