Parallel, Distributed, and Network-Based Processing has undergone impressive change over recent years. New architectures and applications have rapidly become the central focus of the discipline. These changes are often a result of the cross-fertilization of parallel and distributed technologies with other rapidly evolving technologies. It is of paramount importance to review and assess these new developments in comparison with recent research achievements in the well-established areas of parallel and distributed computing, from industry and the scientific community. PDP 2022 will provide a forum for the presentation of these and other issues through original research presentations and will facilitate the exchange of knowledge and new ideas at the highest technical level.

We are organizing a special session in PDP 2022 on "On-chip Parallel and Network-Based Systems". On-chip parallel and network-based system design to achieve functionality with low energy-speed product requires larger device count SoC design, multi-block function design methodology, architectures, and energy evaluation schemes. Such systems, which are emerging as the architecture of choice for future high-performance processors, require high-performance interconnects which are necessary to satisfy the data supply needs of all cores. This session is dedicated to research on on-chip communication technology, architecture, design methods and applications, bringing together scientists and engineers working on on-chip innovations from related research communities, including parallel computer architecture, networking, and embedded systems. Original papers describing new and previously unpublished results are solicited on all aspects of on-chip parallel and networked system technology. Topics of interest include, but are not limited to:

- On-chip network architecture (topology, routing, arbitration, ...)
- Network design for 3D stacked logic and memory
- Processor allocation and scheduling in CMPs
- Mapping of applications onto NoCs
- NoC reliability issues
- OS and compiler support for NoCs
- Performance and power issues in NoCs
- Metrics, benchmarks, and trace analysis for NoCs
- Multi/many-core workload characterization and evaluation
- Modeling and simulation of on-chip parallel and networked systems
- Synthesis, verification, debug and test of SoCs
- NoC support for memory and cache access
- SoC and NoC design methodologies and tools
- Network support for SoC quality of service
- On-chip systems for FPGAs and structured ASICs
- NoC support for CMP/MPSoCs
- Floorplan-aware NoC architecture optimization
- Application-specific NoC design
- Networked SoC case studies
- On-chip parallel programming models and tools
- Reconfigurable SoCs and NoCs
- Memory system design and optimizations for SoCs
- Early reports on system prototypes details
- SIMD parallel VLSI computing
- I/O interconnects and support for SoCs
- and other related topics


Chairs

- H. Sarbazi-Azad, Sharif University of Technology (IRAN)
- N. Bagherzadeh, University of California Irvine (USA)
- A. Tavakkol, Fortum (SWITZERLAND)
- M. Asadinia, Bradley University (USA)


Programme Committee

- H. Asadi, Sharif University of Technology (IRAN)
- F. Angiolini, iNoCS (Switzerland)
- A. Baniasadi, University of Victoria (CANADA)
- M. Bakhouya, Aalto University (FINLAND)
- J. Bourgeois, University of France-Comte (FRANCE)
- S. Evripidou, University of Cyprus (CYPRUS)
- D. Goehringer, Uni­ver­si­ty of Bo­chum (GERMANY)
- T. Hollstein, Tallinn University of Technology (ESTONIA)
- M. Hübner, Uni­ver­si­ty of Bo­chum (GERMANY)
- F. Khunjush, Shiraz University (IRAN)
- A. Khonsari, Tehran University (IRAN)
- S. Koohi, Sharif University of Technology (IRAN)
- S. Kumar, Jönköping University (SWEDEN)
- S. Loucif, ALHOSN University (UAE)
- P. Lotfi Kamran, IPM (IRAN)
- F. Mehdipour, Kyushu University (JAPAN)
- S. Meraji, University of Toronto (CANADA)
- M. Modarressi, Tehran University (IRAN)
- S. Mohammadi, Tehran University (IRAN)
- M. Naderan, University of Gent (BELGIUM)
- A. Nayebi, Google (USA)
- C. Nicopoulus, University of Cyprus (CYPRUS)
- M. Ould-khaoua, University Saad Dahlab of, (ALGERIA)
- M. Palesi, University of Kore (ITALY)
- K. Paul, IIT Delhi (INDIA)
- L. Ramini, University of Ferrara (ITALY)
- V. Rana, Politecnico di Milano (ITALY)
- M. Radezki, Uni­ver­si­ty of Stuttgart(GERMANY)
- F. Rivera , Universidad de Antioquia (COLOMBIA)
- M. Sadrosadati, IPM (IRAN)
- M. Sanchez, Universidad Complutense (SPAIN)
- N. Tabrizi, Kettering University (USA)
- W. Vanderbauwhede, University of Glasgow (UK)
- H.R. Zarandi, Amirkabir University of Technology (IRAN)


Submission Guidelines

Prospective authors should submit a full paper not exceeding 8 pages in the Conference proceedings format (double-column, 10pt) to the conference main track or to the Special Sessions through the EasyChair conference submission system with an indication of the main track or the name of the Special Session.

http://www.easychair.org/conferences/?conf=pdp2021

Double-blind review: the paper should not contain authors' names and affiliations; in the reference list, references to the authors' own work entries should be substituted with the string "omitted for blind review”.

Publication: Proceedings will be published by Conference Publishing Services (CPS). All accepted papers will be included in the same volume, published by the Conference Publishing Services (CPS). The Final Paper Preparation and Submission Instructions will be published after the notification of acceptance. Authors of accepted papers are expected to register and present their papers at the Conference. Conference proceedings will be submitted to IEEE explore, CDSL, and for indexing among others, to DBLP, Scopus ScienceDirect, and ISI Web of Knowledge.