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MTAAP 2011 : Workshop on Multithreaded Architectures and Applications | |||||||||||||||
Link: http://ft.ornl.gov/events/mtaap11/ | |||||||||||||||
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Call For Papers | |||||||||||||||
Theme
Multithreading (MT) programming and execution models, as well as hybrid programming with accelerated architectures, are starting to permeate the high-end and mainstream computing scene. This trend is driven by the need to increase processor utilization and deal with the memory-processor speed gap. Recent and upcoming examples architectures that fit this profile are Cray's XMT, IBM Cyclops, and several SMT processors from Sun (Victoria Falls), IBM (Power6, Power7), or Intel, as well as heterogeneous systems with accelerators such as GPGPUs from ATI, NVIDIA, and Intel. The underlying rationale to increase processor utilization is a varying mix of new metrics that take performance improvements as well as better power and cost budgeting into account. Yet, it remains a challenge to identify and productively program applications for these architectures with a resulting substantial performance improvement. The MTAAP 2011 workshop is a full-day meeting to be held at the IPDPS 2011 focusing on Multithreading architectures and applications. This workshop intends to identify applications that are amenable to MT and the MT programming and execution models as well as the underlying architectures on which they can thrive. The workshop seeks to explore programming frameworks in the form of languages and libraries, compilers, analysis and debugging tools to increase the programming productivity. Topics of interest, of both theoretical and practical significance, include but are not limited to: - Multithreaded Architectures - Heterogeneous architectures including graphics processors and other architectures - Multithreaded Programming Framework - Compilation and Optimization for MT and heterogeneous architectures - Multithreaded Performance Analysis and Debugging Tools - Multithreaded Performance Metrics and Evaluations - Multithreaded Libraries and run-time systems - Innovative applications for MT architectures The MTAAP workshop proceedings will be published along with the IPDPS proceedings. Call for Papers Paper Submission Guidelines Submitted manuscripts may not exceed 15 single-spaced pages using 12-point size font on 8.5x11 inch pages, including figures, tables, and references. Please use the standard 1-inch margin. Authors may submit additional material as an appendix to their submission, but there is no guarantee that this material will influence the review process. Manuscripts must be submitted electronically and in PDF format. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers may not have appeared in or be under consideration for another workshop, conference, or journal. MTAAP submissions are being handled by EDAS system. To submit a paper, please use the following link (MTAAP EDAS) and follow the instructions. Important Dates Papers due: 10 Jan 2011 Notification of acceptance: 7 Feb 2011 Camera-ready due: 21 Feb 2011 (strict deadline set by IPDPS; no extensions) Proceedings The proceedings of this workshop will be published together with the proceedings of other IPDPS 2010 workshops by the IEEE Computer Society Press. Workshop Archive Information and papers from the earlier MTAAP workshops are available: 2010 MTAAP 2009 MTAAP Workshop Organization Chairs Luiz DeRose (Cray) (ldr@cray.com) Jeffrey Vetter (ORNL and Georgia Tech) (vetter@computer.org) Tentative Program Committee Sadaf Alam (CSCS) David Bader (Georgia Tech) Jonathan Berry (Sandia National Laboratory) Daniel Chavarria (Pacific Northwest National Laboratory) John Feo (Pacific Northwest National Laboratory) Guang Gao (U. Delaware) Mahantesh Halappanavar (Pacific Northwest National Laboratory) Bruce Hendrickson (Sandia National Laboratory) Larry Kaplan (Cray) Peter Kogge (Notre Dame) Michael Merrill (DoD) Jose Moreira (IBM) P. Sadyappan (Ohio State) Mateo Valero (Universitat Politecnica de Catalunya) |
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