Deadline extension December 15, 2018.

Introduction.

Data-level parallelism (DLP) and thread-level parallelism (TLP) are keystones to achieve Exascale computing under a reasonable power budget. Both DLP and TLP are present in most modern supercomputers, regardless of being based on accelerators (e.g., GPGPUs) and/or CPUs (IBM Vector Media eXtension –VMX–, NEC SX architecture, Intel Advanced Vector eXtension –AVX– and ARM Scalable Vector Extension –SVE–).

This special issue at the Journal of Supercomputing (ISSN: 0920-8542, JCR Q2 1.532 Impact Factor) is looking for original research works to explore the intersection between both algorithm design and hardware improvements to deal with the emergent challenges of the upcoming vector applications. In this regard, one of the main objectives of this special issue proposal is discussing about the main trends in vector parallel processing, algorithm definition and problem-domain requirements altogether, which may anticipate future solutions to be translated into real benefits to the society.

Topics

The goal of this special issue is to present the readers with novel hardware enhancements, vectorization tools, codes and strategies as well as current (and future) trends in vector architectures (CPUs, GPUs or accelerators). Our goal is to cover the full development stack, from applications to hardware. The target audience will be application developers as well as academy and industry researchers interested in improving vector codes and vector architectures. Topics of interest, of both theoretical and practical significance, include but are not limited to vector (CPU, GPU or accelerators):

- Programming framework
- Programming model and language explorations
- Compilation and optimization - including algorithmic improvements and code optimization
- Performance Analysis and Debugging Tools
- Performance Metrics and Evaluations
- Libraries and run-time systems
- Design, generation, verification and validation of representative applications
- Case-studies of representative applications
- Innovative applications for vector architectures
- Hardware studies and micro-architectural implementation tradeoffs

Important Dates

- Submission Due December 15, 2018

Information for Authors

VAAEE Special Issue will follow the Journal of Supercomputing format templates available here (http://static.springer.com/sgw/documents/468198/application/zip/LaTeX_DL_468198_220518.zip).

Each article must not exceed 18 pages following the aforementioned template, including references.

To submit your article follow the regular submission procedure for the JSC Jorunal and then select the S.I. : Vector Architectures and Applications in the Exascale Era as submission target instead of regular submission.

Please check further details about Information for Authors at JSC webpage (https://www.springer.com/computer/swe/journal/11227).