VTS: VLSI Test Symposium



Past:   Proceedings on DBLP

Future:  Post a CFP for 2022 or later   |   Invite the Organizers Email


All CFPs on WikiCFP

Event When Where Deadline
VTS 2021 39th IEEE VLSI Test Symposium
Apr 25, 2021 - Apr 28, 2021 Virtual Interactive Live Event Nov 14, 2020 (Nov 7, 2020)
VTS 2020 IEEE VLSI Test Symposium
Apr 5, 2020 - Apr 8, 2020 San Diego Oct 11, 2019 (Oct 4, 2019)
VTS 2015 VLSI Test Symposium
Apr 27, 2015 - Apr 29, 2015 Napa, California, USA Nov 7, 2014
VTS 2014 The IEEE VLSI Test Symposium
Apr 13, 2014 - Apr 17, 2014 Napa, California Oct 25, 2013 (Oct 18, 2013)
VTS 2013 IEEE 31st VLSI Test Symposium
Apr 29, 2013 - May 2, 2013 Berkeley, USA Oct 19, 2012
VTS 2011 IEEE VlSI Test Symposium
May 1, 2011 - May 5, 2011 Dana Point, USA Sep 19, 2010

Present CFP : 2021


The IEEE VLSI Test Symposium (VTS) explores emerging trends and novel concepts in test, validation, yield, reliability and security of microelectronic circuits and systems. The 2021 edition of VTS will be an online virtual interactive live event.

The program includes keynotes, scientific paper presentations, short industrial application paper presentations, special sessions and Innovative Practices sessions.

Given the unique opportunity of reaching the worldwide test community through a virtual event registration rate for most authors and attendees will be a fraction of our registration rate for VTS’20.

You are invited to participate and submit your contributions to VTS’21. The areas of interest include (but are not limited to) the following topics:

* Analog, Mixed-Signal, RF Test
* ATPG & Compression
* Silicon Debug
* Automotive Test & Safety
* Built-In Self-Test (BIST)
* Defect & Current Based Test
* Defect & Fault Tolerance
* Delay & Performance Test
* Design for Testability, Yield or Reliability
* Pre-silicon Design Verification & Validation
* Post-silicon Validation
* Embedded System & Board Test
* Embedded Test Methods
* Emerging Technologies Test and Reliability
* FPGA Test
* Fault Modeling and Simulation
* Hardware Security
* Low-Power IC Test
* Machine Learning in Test,Yield and Reliability
* Microsystems/MEMS/Sensors Test
* Memory Test and Repair
* On-Line Test & Error Correction
* Power & Thermal Issues in Test
* System-on-Chip (SOC) Test
* Test & Reliability of Biomedical Devices
* Test & Reliability of High-Speed I/O
* Test & Reliability of Machine Learning Systems
* Test Quality & Reliability
* Test Standards & Economics
* Test Resource Partitioning
* Transient & Soft Errors
* 2.5D, 3D & SiP Test
* Yield Optimization

New hot topics:

VTS puts particular emphasis on enlarging its scope soliciting submissions on aspects on the following hot topics:
- Test, Reliability & Security of AI and Neuromorphic Devices
- Machine Learning for Test
- Test & Reliability of Machine Learning Systems
- Test, Reliability & Security in Quantum Computing

Key Dates:
Paper registration (title, abstract and authors): November 7, 2020
Paper PDF upload: November 14, 2020
Questions from reviewers to authors: December 11, 2020
Submission of rebuttal: December 15, 2020
Notification of acceptance: December 21, 2020


The VTS Program Committee invites original, unpublished submissions in the following categories:

- Scientific Papers: complete manuscripts, up to six pages (EXCLUDING THE BIBLIOGRAPHY) in a standard IEEE two-column format. Papers exceeding the page limit will be returned without review. Authors should clearly explain the significance of the work, highlight novel features, and describe its current status.

- Industrial applications short papers: short papers, up to three pages (EXCLUDING THE BIBLIOGRAPHY) presenting relevant industrial applications or practices.
Special session proposals: proposals for special sessions may include presentations on hot topics, panels, embedded tutorials. Every proposal must include a 150-to-200 word abstract the name of the organizers and a list of at least three speakers with a tentative presentation title. If the proposal for the special session is accepted, speakers and organizers will be invited to prepare a paper, up to ten pages (excluding references) to be included in the formal proceedings of the conference.

- Proposals for the Innovative Practices sessions: The innovative practices track highlights cutting-edge challenges faced by test practitioners in the industry, and innovative solutions employed to address them. Every proposal must include a 150-to-200 word abstract the name of the organizers and a list of at least three speakers with a tentative presentation title. If the proposal for the special session is accepted, speakers and organizers will be invited to prepare a one page abstract describing the content of the session to be included in the formal proceedings of the conference.

All submissions must be submitted electronically through the VTS website. A submission will be considered as evidence that, upon acceptance, the author(s) will submit a final camera-ready version of the paper. Registration of at least one author by the camera-ready deadline and presentation of the paper at the symposium are also required for inclusion of the paper in the published proceedings.

Starting from 2021 VTS review process for both scientific papers and industrial application short papers is DOUBLE BLIND with REBUTTAL. The page limit excludes the Bibliography.

Do not include any author names on any submitted documents except in the space provided on the submission form. You must also ensure that the metadata included in the PDF does not give away the authors. If you are improving upon your prior work, refer to your prior work in the third person and include a full citation for the work in the bibliography.

Authors will be required to answer specific questions from the reviewers in a rebuttal phase before the TPC meeting.

For general information:
General Co-chairs
Lorena Anghel (SPINTEC, Grenoble INP) (lorena.anghel@grenoble-inp.fr)
Stefano Di Carlo (Politecnico di Torino) (stefano.dicarlo@polito.it)

For submission-related information:
Program Co-chairs
Mehdi Tahoori (KIT) (tahoori@ira.uka.de)
Suriyaprakash Natarajan (Intel) (suriyaprakash.natarajan@intel.com)

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