SLIP: System-Level Interconnect Prediction

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Past:   Proceedings on DBLP

Future:  Post a CFP for 2020 or later   |   Invite the Organizers Email

 
 

All CFPs on WikiCFP

Event When Where Deadline
SLIP 2019 International Workshop on System-Level Interconnect Prediction
Jun 2, 2019 - Jun 2, 2019 Las Vegas, NV Mar 29, 2019 (Mar 22, 2019)
SLIP 2018 20th IEEE/ACM International Workshop on System-Level Interconnect Prediction
Jun 23, 2018 - Jun 23, 2018 San Francisco Mar 18, 2018 (Mar 11, 2018)
SLIP 2013 International Workshop on System Level Interconnect Prediction
Jun 2, 2013 - Jun 2, 2013 Austin, TX, USA TBD
SLIP 2012 International Workshop on System Level Interconnect Prediction
Jun 3, 2012 - Jun 3, 2012 San Francisco, CA, USA Mar 5, 2012 (Feb 27, 2012)
SLIP 2011 System Level Interconnect Prediction 2011
Jun 5, 2011 - Jun 5, 2011 San Diego, CA Mar 11, 2011 (Mar 4, 2011)
SLIP 2010 System-Level Interconnect Prediction
Jun 13, 2010 - Jun 13, 2010 Anaheim Mar 4, 2010 (Feb 26, 2010)
SLIP 2008 International Workshop on System Level Interconnect Prediction
Apr 5, 2008 - Apr 6, 2008 Newcastle, United, Kngdm Dec 7, 2007
 
 

Present CFP : 2019

Call for Papers

The 21st IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2019)

Las Vegas Convention Center, Nevada, United States, June 2, 2019

Co-located with DAC 2019

Co-sponsored by the ACM SIGDA and the IEEE Computer Society

http://www.sliponline.org/

Overview: The ever-increasing complexity of modern networks shifts the design focus towards the interconnect driven challenges across all the levels of design abstraction. Advancements in design and prediction of highly interconnected systems are critical to markets such as intelligent autonomous transportation, innovative health care, sophisticated security systems, artificial bio-inspired networks, Internet of Things, and high-performance computing. The IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP) is a unique opportunity to engage with experts from academia, industry, and government, specializing in a broad scope of interconnect prediction techniques, from applications to architectural and micro-architectural exploration to physical design, interconnect technology planning, and communication networks. Keynote talk will be given by Prof. Andrew B. Kahng, UC San Diego. In addition to the presentation of state-of-the-art papers in these fields, invited talks and panels by leading researchers will aim to encourage dialogue between the architecture, physical design, and interconnect technology communities.



SLIP 2019 is the 21st IEEE/ACM International Workshop on System-Level Interconnect Prediction. The workshop is collocated with the Design Automation Conference (DAC) 2019 in Las Vegas, Nevada, USA. Manuscripts that contain late-breaking results, works-in-progress, design frameworks, and conceptual papers are all will be considered. All accepted papers are expected to be included in both ACM and IEEE Xplore libraries. In addition, we highly encourage researchers and developers to submit proposals for tutorials. SLIP 2019 is co-sponsored by ACM SIGDA and the IEEE Computer Society.



Workshop Scope: Topics of interest include, but are not limited to:

• Learning and predictive models for optimizing interconnect at various IC/system design stages

• System-level design for FPGAs, NoCs, reconfigurable systems

• Design, analysis, and (co)optimization of power and clock networks

• Topologies and fabrics of multi- and many-core architectures

• Power consumption of interconnects

• System level reliability, aging, and thermal issues

• Security-aware power/clock delivery and interconnect design

• Design-for-manufacturing (DFM) and yield techniques for interconnects

• High speed chip-to-chip interconnect

• Design and analysis of chip-package interfaces

• 3D interconnect design and prediction

• Applications of interconnects to social, genetic, and biological systems

• Bio-inspired connectionist systems, such as artificial neural networks

• Other complex networks and high-performance computing

• Emerging interconnect technologies in machine learning platforms & chips



Paper Submission Guidelines

Submissions should contain significant novel ideas and technical results that have not been published or concurrently submitted to any other venue. Submitted manuscripts of 4 to 8 pages should be written in English conforming to the ACM or IEEE conference proceedings format (double-columned, 9pt or 10pt font, 8.5”x11” page size). All paper submissions must represent original and unpublished work. To permit double blind review, all papers must remove author information (submissions with author information will be rejected). Papers must be submitted electronically as PDF files through EasyChair website: https://easychair.org/conferences/?conf=slip2019.

Important Dates

Abstract submission: March 22, 2019

Paper/tutorial submission: March 29, 2019

Author notification: April 7, 2019

Final version upload: April 21, 2019

Conference: June 2, 2019

Organizing Committee

General Chair:

Selçuk Köse, University of Rochester, USA



Technical Program Chair:

Inna P.-Vaisband, University of Illinois at Chicago, USA



Technical Program Co-Chair:

Mingsong Chen, East China Normal University, China



Finance Chair:

Weize Yu, Old Dominion University, USA



Publicity Chairs:

Ming-Chang Yang, Chinese University of Hong Kong, Hong Kong

Boris Vaisband, University of California, Los Angeles, USA



Panel Chair:

Shantanu Dutt, University of Illinois at Chicago, USA



Publications Chair:

Junlong Zhou, Nanjing University of Science and Technology, China
 

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