All CFPs on WikiCFP
Present CFP : 2020
The SC Papers program is the leading venue for presenting high-quality original research, groundbreaking ideas, and compelling insights on future trends in high performance computing, networking, storage, and analysis. Technical papers are peer-reviewed and an Artifact Description is mandatory for all papers submitted to SC20. Submissions will be considered on any topic related to high performance computing within the nine areas below. Small-scale studies – including single-node studies –are welcome as long as the paper clearly conveys the work’s contribution to high-performance computing.
The development, evaluation, and optimization of scalable, general-purpose, high performance algorithms.
Algorithms for discrete and combinatorial optimization
Algorithms for hybrid and heterogeneous systems with accelerators
Algorithms for numerical methods and algebraic systems
Data-intensive parallel algorithms
Energy- and power-efficient algorithms
Graph and network algorithms
Load balancing and scheduling algorithms
Uncertainty quantification methods
Other high performance computing algorithms
The development and enhancement of algorithms, parallel implementations, models, software and problem solving environments for specific applications that require high performance resources.
Bioinformatics and computational biology
Computational earth and atmospheric sciences
Computational materials science and engineering
Computational astrophysics/astronomy, chemistry, and physics
Computational fluid dynamics and mechanics
Computation and data enabled social science
Computational design optimization for aerospace, energy, manufacturing, and industrial applications
Computational medicine and bioengineering
Improved models, algorithms, performance or scalability of specific applications and respective software
Use of uncertainty quantification, statistical, and machine-learning techniques to improve a specific HPC application
Other high performance applications
Architecture and Networks
All aspects of high performance hardware including the optimization and evaluation of processors and networks.
Architectures to support extremely heterogeneous composable systems (e.g., chiplets)
Design-space exploration / Performance projection for future systems
Evaluation and measurement on testbed or production hardware systems
Hardware acceleration of containerization and virtualization mechanisms for HPC
Interconnect technologies, topology, switch architecture, optical networks, software-defined networks
I/O architecture/hardware and emerging storage technologies
Memory systems: caches, memory technology, non-volatile memory, memory system architecture (to include address translation for cores and accelerators)
Multi-processor architecture and micro-architecture (e.g. reconfigurable, vector, stream, dataflow, GPUs, and custom/novel architecture)
Network protocols, quality of service, congestion control, collective communication
Power-efficient design and power-management strategies
Resilience, error correction, high availability architectures
Scalable and composable coherence (for cores and accelerators)
Secure architectures, side-channel attacks, and mitigation
Software/hardware co-design, domain specific language support
Clouds and Distributed Computing
Cloud and system software architecture, configuration, optimization and evaluation, support for parallel programming on large-scale systems or building blocks for next-generation HPC architectures.
HPC, cloud, and edge computing convergence at infrastructure and software level, including service-oriented architectures and tools
Job/workflow scheduling, load balancing, resource provisioning, energy efficiency, fault tolerance, and reliability
Methods, systems, and architectures for big data and data stream processing in HPC and cloud systems
OS/runtime and system-software enhancements for many-core systems, accelerators, complex memory space/hierarchies, I/O, and network structures
Parallel programming models and tools at the intersection of cloud, edge, and HPC
Self-configuration, management, information services, monitoring, and introspective system software
Security and identity management in HPC and cloud systems
Scalable HPC and machine learning case studies on distributed and/or cloud systems
Virtualization and containerization to support HPC and emerging uses such as machine learning
Data Analytics, Visualization, and Storage
All aspects of data analytics, visualization, storage, and storage I/O related to HPC systems. Submissions on work done at scale are highly favored.
Cloud-based analytics at scale
Databases and scalable structured storage for HPC
Data mining, analysis, and visualization for modeling and simulation
Data analytics and frameworks supporting data analytics
Ensemble analysis and visualization
I/O performance tuning, benchmarking, and middleware
Next-generation storage systems and media
Parallel file, object, key-value, campaign, and archival systems
Provenance, metadata, and data management
Reliability and fault tolerance in HPC storage
Scalable storage, metadata, namespaces, and data management
Storage tiering, entirely on-premise internal tiering as well as tiering between on-premise and cloud
Storage innovations using machine learning such as predictive tiering, failure, etc.
Scalable Cloud, Multi-Cloud, and Hybrid storage
Storage systems for data-intensive computing
Machine Learning and HPC
The development and enhancement of algorithms, systems, and software for scalable machine learning utilizing high-performance and cloud computing platforms.
ML for HPC / HPC for ML
Data parallelism and model parallelism
Efficient hardware for machine learning
Hardware-efficient training and inference
Performance modeling of machine learning applications
Scalable optimization methods for machine learning
Scalable hyper-parameter optimization
Scalable neural architecture search
Scalable IO for machine learning
Systems, compilers, and languages for machine learning at scale
Testing, debugging, and profiling machine learning applications
Visualization for machine learning at scale
Performance Measurement, Modeling, and Tools
Novel methods and tools for measuring, evaluating, and/or analyzing performance for large scale systems.
Analysis, modeling, or simulation methods for performance
Methodologies, metrics, and formalisms for performance analysis and tools
Novel and broadly applicable performance optimization techniques
Performance studies of HPC hardware and software subsystems such as processor, network, memory, accelerators, and storage
Scalable tools and instrumentation infrastructure for measurement, monitoring, and/or visualization of performance
System-design tradeoffs between performance and other metrics (e.g., performance and resilience, performance and security)
Workload characterization and benchmarking techniques
Technologies that support parallel programming for large-scale systems as well as smaller-scale components that will plausibly serve as building blocks for next-generation HPC architectures.
Compiler analysis and optimization; program transformation
Parallel programming languages, libraries, models, and notations
Parallel application frameworks
Programming language and compilation techniques for reducing energy and data movement (e.g., precision allocation, use of approximations, tiling)
Program analysis, synthesis, and verification to enhance cross-platform portability, maintainability, result reproducibility, resilience (e.g., combined static and dynamic analysis methods, testing, formal methods)
Runtime systems as they interact with programming systems
Solutions for parallel-programming challenges (e.g., interoperability, memory consistency, determinism, race detection, work stealing, or load balancing)
Tools for parallel program development (e.g., debuggers and integrated development environments)
State of the Practice
All R&D aspects of the pragmatic practices of HPC, including operational IT infrastructure, services, facilities, large-scale application executions and benchmarks.
Bridging of cloud data centers and supercomputing centers
Comparative system benchmarking over a wide spectrum of workloads
Containers at scale: performance and overhead
Deployment experiences of large-scale infrastructures and facilities
Facilitation of “big data” associated with supercomputing
Infrastructural policy issues, especially international experiences
Long-term infrastructural management experiences
Pragmatic resource management strategies and experiences
Procurement, technology investment and acquisition best practices
Quantitative results of education, training and dissemination activities
Software engineering best practices for HPC
User support experiences with large-scale and novel machines
Reproducibility of data
Preparing Your Submission
A paper submission has three components: the paper itself, an Artifact Description Appendix (AD), and an Artifact Evaluation Appendix (AE). The Artifact Description Appendix, or explanation of why there is no artifact description, is mandatory. The Artifact Evaluation Appendix is optional.
Papers that have not previously been published in peer-reviewed venues are eligible for submission to SC. For example, papers pre-posted to arXiv, institutional repositories, and personal websites (but no other peer-reviewed venues) remain eligible for SC submission. Papers that were published in a workshop are eligible if they have been substantially enhanced (i.e. 30% new material).
Submissions are limited to 10 pages, excluding the bibliography, using the IEEE proceedings template, with line numbering enabled to help with review.
AD and AE appendices are automatically generated and do not count against the 10 pages.
Authors must indicate a primary area from the choices on the submissions form and are strongly encouraged to indicate a secondary area.
Where to Submit
Papers are submitted via the SC submissions website. View a sample form.
Transparency and Reproducibility Initiative
We believe that reproducible science is essential, and that SC continues to innovate in this area. For SC20 there will be greater integration of the AD/AE Appendices into the review process with AD/AE Appendices considered at every stage of paper review. AD/AE Appendices will continue to be auto-generated from author responses to a standard form that is embedded in the SC online submission system. While the Artifact Description Appendix, or explanation of why there is no Artifact Description Appendix, is mandatory, the Artifact Evaluation Appendix continues to be optional. Learn more about the Transparency and Reproducibility Initiative.
Papers are peer-reviewed by a committee of experts. Each paper will have three to four reviews. The peer review is a double-blind process. Reviewers do not have access to the names of authors. While Papers Committee members are named on the SC20 Planning Committee page, the names of the individuals reviewing each paper are not made available to the paper authors. Learn more about the SC double-blind review policy, and see examples in the Papers FAQ (Available Winter 2020).
Review, Response, Revision
From an author’s perspective, the following are the key steps:
Authors submit a title, abstract, and other metadata.
Authors submit their full paper and complete an AD/AE form describing their computational artifacts (or lack of computational artifacts) and, optionally, text discussing how they evaluated their computational results.
Papers not respecting the submission guidelines will be subject to immediate reject without review. For example, papers not respecting the double-blind submission or papers exceeding the page limit.
Authors receive an initial set of reviews of their paper. Papers not reaching the minimum quality criteria to go to the second review stage will be rejected at this point. Early rejection will allow authors to revise and resubmit their papers to other venues.
Authors of papers that reach the second review stage have an opportunity to revise their paper and prepare an accompanying response to the reviewers.
Author revisions and accompanying response will be available to the reviewers at least a week before the Papers Committee meeting.
Authors are notified of their paper’s status: Accept, Reject, or Major Revisions Required.
In the case of Major Revisions Required, authors prepare a major revision for a third stage review.
After the third stage review, the paper will be either accepted or rejected.
Authors of accepted papers prepare the final version of their paper.
Conflict of Interest
Please review the SC Conference Conflict of Interest guidelines before submitting your paper.
Please see the IEEE guidelines on identifying plagiarism. Authors should submit new, original work that represents a significant advance from even their own prior publications.
If your Paper is selected, at least one author must register for the Technical Program in order to attend the SC Conference and present the paper.
Finalizing Accepted Papers
Upon acceptance, all Papers (including those that goes through major revisions) will be listed in the online SC Schedule. We expect this to happen at the end of August 2020.
Papers are archived in the ACM Digital Library and IEEE Xplore; members of SIGHPC or subscribers to the archives may access the full papers without charge. This publication contains the full text of all Papers and their Artifact Description appendices presented at the SC Conference.
Schedule and Location
Papers presentations will be held Tuesday–Thursday, November 17–19, 2020. Papers sessions are 30 minutes. Day, time, and location for each paper session will be published in the online SC Schedule by August.
Papers are assigned either a classroom or a theater room equipped with standard AV facilities:
Microphone and podium
Wireless lapel microphone or wireless handheld microphone
Best Paper (BP) and Best Student Paper (BSP) nominations are made during the review process and are highlighted in the online SC schedule. BP and BSP winners are selected at the conference by a committee who attends the corresponding paper presentations, and winners are announced at the Thursday Awards ceremony.