ASP-DAC: Asia and South Pacific Design Automation Conference

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Past:   Proceedings on DBLP

Future:  Post a CFP for 2022 or later   |   Invite the Organizers Email

 
 

All CFPs on WikiCFP

Event When Where Deadline
ASP-DAC 2021 26th Asia and South Pacific Design Automation Conference
Jan 18, 2021 - Jan 21, 2021 Tokyo Odaiba Waterfront, Japan Jul 26, 2020
ASP-DAC 2019 24th Asia and South Pacific Design Automation Conference
Jan 21, 2019 - Jan 24, 2019 Tokyo, Japan Jul 6, 2018
ASP-DAC 2018 23rd Asia and South Pacific Design Automation Conference
Jan 22, 2018 - Jan 25, 2018 Jeju Island , Korea Jul 7, 2017
ASP-DAC 2016 Asia and South Pacific Design Automation Conference
Jan 25, 2016 - Jan 28, 2016 Macao, China Jul 8, 2015
ASP-DAC 2015 Asia and South Pacific Design Automation Conference
Jan 19, 2015 - Jan 22, 2015 Makuhari, Japan Jul 11, 2014
ASP-DAC 2014 Asia and South Pacific Design Automation Conference
Jan 20, 2014 - Jan 23, 2014 SunTec,Singapore Jul 10, 2013
ASP-DAC 2012 17th Asia and South Pacific Design Automation Conference
Jan 30, 2012 - Feb 2, 2012 Sydney, Australia Jul 19, 2011
ASP-DAC 2011 16th Asia and South Pacific Design Automation Conference
Jan 25, 2011 - Jan 28, 2011 Yokohama, Japan Jul 19, 2010
ASP-DAC 2010 Asia and South Pacific Design Automation Conference
Jan 18, 2010 - Jan 21, 2010 Taipei, Taiwan Aug 3, 2009
ASP-DAC 2009 14th Asia and South Pacific Design Automation Conference
Jan 19, 2009 - Jan 22, 2009 Yokohama, Japan Jul 14, 2008
ASP-DAC 2008 Asia and South Pacific Design Automation Conference
Jan 21, 2008 - Jan 24, 2008 Seoul, South, Korea Nov 16, 2007
 
 

Present CFP : 2021

Aims of the Conference:
ASP-DAC 2021 is the 26th annual international conference on VLSI design automation in Asia and South Pacific regions, one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.

Areas of Interest:
Original papers in, but not limited to, the following areas are invited.

1. System-Level Modeling and Design Methodology:
1.1. HW/SW co-design, co-simulation and co-verification
1.2. System-level design exploration, synthesis, and optimization
1.3. System-level formal verification
1.4. System-level modeling, simulation and validation tools/methodology

2. Embedded Systems and Cyberphysical Systems:
2.1. Many- and multi-core SoC architecture
2.2. IP/platform-based SoC design
2.3. Domain-specific architecture
2.4. Dependable architecture
2.5. Cyber physical system
2.6. Internet of things

3. Embedded Systems Software:
3.1. Kernel, middleware, and virtual machine
3.2. Compiler and toolchain
3.3. Real-time system
3.4. Resource allocation for heterogeneous computing platform
3.5. Storage software and application
3.6. Human-computer interface

4. Memory Architecture and Near/In Memory Computing:
4.1. Storage system and memory architecture
4.2. On-chip memory architectures and management: Scratchpads, compiler, controlled memories, etc.
4.3. Memory and storage hierarchies with emerging memory technologies
4.4. Near-memory and in-memory computing
4.5. Memory architecture and management for emerging memory technologies

5. AI/Machine Learning System Designs:
5.1. Hardware and devices for neuromorphic and neural network computing
5.2. Design method for learning on a chip
5.3. Systems for neural computing (including deep neural networks)
5.4. Neural network acceleration co-design techniques
5.5. Design techniques for AI of Things

6. Analog/Mixed-Signal Design, Simulation and Validation:
6.1. Analog/mixed-signal/RF synthesis
6.2. Analog layout, verification, and simulation techniques
6.3. High-frequency electromagnetic simulation of circuit
6.4. Mixed-signal design consideration
6.5. Communication architectures using nanophotonics, RF, 3D, etc.
6.6. Networks-on-chip and NoC-based system design

7. Approximate, Stochastic and Neuromorphic Computing:
7.1. Circuit and system techniques for approximate computing
7.2. Stochastic computing for AI/ML
7.3. CAD for approximate and stochastic systems
7.4. Neuromorphic computing for AI/ML
7.5. CAD for bio-inspired and neuromorphic systems

8. Logic/High-Level Synthesis and Optimization:
8.1. High-level synthesis tool and methodology
8.2. Combinational, sequential and asynchronous logic synthesis
8.3. Logic synthesis and physical design technique for FPGA
8.4. Technology mapping

9. Physical Design:
9.1. Floorplanning, partitioning and placement
9.2. Interconnect planning and synthesis
9.3. Placement and routing optimization
9.4. Clock network synthesis
9.5. Post layout and post-silicon optimization
9.6. Package/PCB/3D-IC routing

10. Design for Manufacturability and Reliability:
10.1. Reticle enhancement, lithography-related design and optimization
10.2. Resilience under manufacturing variation
10.3. Design for manufacturability, yield, and defect tolerance
10.4. Reliability, aging and soft error analysis
10.5. Design for reliability, aging, and robustness
10.6. Machine learning for smart manufacturing and process control

11. Design and Analysis for Timing and Low Power:
11.1. Power modeling, analysis and simulation
11.2. Low-power design and optimization at circuit and system levels
11.3. Thermal aware design and dynamic thermal management
11.4. Energy harvesting and battery management
11.5. Deterministic/statistical timing analysis and optimization
11.6. 2D/3D on-chip power/ground and package modeling, analysis and optimization
11.7. Signal/power integrity, EM modeling and analysis
11.8. Extraction, TSV and package modeling

12. Testing, Validation, Simulation, and Verification:
12.1. ATPG, BIST and DFT
12.2. System test and 3D IC test
12.3. Online test and fault tolerance
12.4. Memory test and repair
12.5. RTL and gate-leveling modeling, simulation, and verification
12.6. Circuit-level formal verification
12.7. Device/circuit-level simulation tool and methodology

13. Hardware and Embedded Security:
13.1. Hardware-based security
13.2. Detection and prevention of hardware Trojans
13.3. Side-channel attacks, fault attacks and countermeasures
13.4. Design and CAD for security
13.5. Cyberphysical system security
13.6. Nanoelectronic security
13.7. Supply chain security and anti-counterfeiting

14. Emerging Technologies and Applications:
14.1. Biomedical, biochip, and biodata processing
14.2. Big/thick data, datacenter
14.3. Advanced multimedia application
14.4. Energy-storage/smart-grid/smart-building design and optimization
14.5. Automotive system design and optimization
14.6. New transistor/device and process technology: spintronic, phase-change, single-electron etc.
14.7. Nanotechnology, MEMS, quantum computing etc.

Please note that each paper shall be accompanied by at least one different conference registration at the speaker’s registration rate (e.g., two speaker registrations are needed for presenting two accepted papers). But any registered co-author can present the work at the conference. ACM and IEEE reserve the right to exclude a paper from distribution after the conference (e.g., removal from ACM Digital Library and IEEE Xplore) if the paper is not presented at the conference by the author of the paper. ASP-DAC does not allow double and/or parallel submissions of similar work to any other conferences, symposia, and journals.
 

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