ISLPED 2026 Call for Papers

Important Dates (Tentative)
Technical Papers (11:59 PST)
Abstract registration: March 2, 2026
Full paper: March 9, 2026
Invited Talk, Tutorial, and Special Session Proposals April 6, 2026
Design Contest Applications May 11, 2026
Notification of Acceptance May 18, 2026
Camera-ready Submission June 15, 2026

Track 1. Technology, Circuits, and Architecture
1.1. Technologies and Circuits
Low-power technologies for device, interconnect, logic, memory, 2.5/3D, cooling, harvesting, sensors, optical, printable, biomedical, battery, and alternative energy storage devices and technology enablers for non-Boolean and quantum/quantum-inspired compute models. Lowpower circuits for logic, memory, reliability, yield, clocking, resiliency; low-power analog/mixed-signal circuits for wireless, RF, MEMS, ADC/DAC, I/O, PLLs/DLLs, DC-DC converters; energy-efficient circuits for emerging applications (e.g., neuromorphic, biomedical, in-vitro sensing, autonomous); circuits using emerging technologies; cryogenic circuits. DTCO for low power; combinatorial optimizers (Ising machine). AI/ML-based circuit optimization; circuit architecture for power-efficient AI applications.

1.2. Logic and Architecture
Low-power logic and microarchitecture for SoC designs, processor cores (compute, graphics, and other special purpose cores), cache, memory, arithmetic/signal processing, cryptography, variability, asynchronous design, and non-conventional computing. System technology co-optimization (STCO) for low power. AI/ML-assisted logic optimization and architecture exploration. Power efficient architecture for AI.

Track 2. EDA, Systems, and Software
2.1. CAD Tools and Methodologies
CAD tools, methodologies, and AI/ML-based approaches for low power and thermal-aware design (analog/digital). AI/ML for acceleration of IP block design convergence. Power estimation, optimization, reliability, and variation impact on power optimization at all levels of design abstraction: physical, circuit, gate, register transfer, behavior, and algorithm.

2.2. Systems and Platforms
Low-power, power-aware, and thermal-aware system design including data centers, SoCs, embedded systems, Internet-of-Things (IoT), wearable computing, body-area networks, wireless sensor networks, and system-level power implications due to reliability and variability. Applications of AI/ML-based solutions and brain-inspired computing to power-aware system and platform design.

2.3. Software and Applications
Energy-efficient, energy/thermal-aware software and application design, including scheduling and management, power optimization through HW/SW co-design, and emerging low-power AI/ML applications.

2.4. Hardware and System Security
Low-power hardware security primitives (PUF, TRNG, cryptographic/post-quantum cryptographic accelerators), nano-electronics security, supply chain security, IoT security and AI/ML security; confidential computing; energy-efficient approaches to system security.

Track 3. AI/ML, Quantum and Emerging Hardware
3.1. Analog, Mixed-Signal & Emerging AI Hardware
Analog and mixed-signal computing architectures for AI/ML including analog matrix multiplication, in-memory computing, and compute-inmemory techniques; emerging device technologies such as memristors, ReRAM, phase-change memory, and photonic computing; neuromorphic and brain-inspired computing systems including spiking neural networks; circuit design techniques for analog AI accelerators including ADC/DAC design, switched-capacitor networks, and noise-resilient architectures; EDA tools and methodologies for analog/mixedsignal AI systems including simulation, verification, and layout automation; process variation mitigation and robustness techniques for nonideal analog computation.

3.2. Digital AI Hardware & Systems
Digital accelerator architectures including systolic arrays, dataflow architectures, and tensor processing units; ASIC, FPGA, and GPU-based implementations for AI/ML workloads; memory hierarchy design and optimization including high-bandwidth memory, scratchpads, and cache architectures; sparse computation and quantization hardware; RTL design, verification, and synthesis for AI accelerators; logic synthesis, place-and-route, timing closure, and power optimization for ML chips; system-level design including network-on-chip, interconnects, and multi-chip systems; compiler, runtime, and systems software for AI hardware; performance modeling, simulation, and design space exploration tools.

3.3. Quantum Computing and Emerging Computing Technologies
Quantum computing hardware platforms including superconducting qubits, trapped ions, and photonic systems; quantum algorithms, error correction, and fault tolerance; quantum circuit compilation and optimization; NISQ algorithms and hybrid quantum-classical systems; emerging post-CMOS paradigms including DNA computing, molecular computing, photonic computing, and probabilistic computing; neuromorphic and spin-based computing; EDA tools, programming frameworks, and benchmarking methodologies for quantum and emerging computing platforms.

Track 4. Industrial Design Track
This track solicits papers to reinforce interaction between the academic research community and industry. Industrial Design track papers have the same submission deadline as regular papers and should focus on similar topics but are expected to provide a complementary perspective to academic research by focusing on challenges, solutions, and lessons learnt while implementing industrial-scale designs.




Submissions (not published/accepted/under review by another journal, conference, symposium, or workshop) should be full-length papers of up to 6 pages (PDF format, double-column, US letter size, using the ACM Conference format available at https://www.acm.org/publications/proceedings-template) including all illustrations, tables, and an abstract of no more than 250 words, plus an additional 1 page for references only.

Accepted papers will be submitted to the IEEE Xplore Digital Library and the ACM Digital Library. ISLPED’26 will present three Best Paper Awards based on the ratings of reviewers and a panel of judges. Selected papers will be invited to submit an extended version for publication in the IEEE Transactions on Very Large Scale Integration.


There will be several invited talks by industry and academic thought leaders on key issues in low-power electronics and design. The Symposium may also include embedded tutorials to provide attendees with the necessary background to follow recent research results, as well as panel discussions on future directions in low-power electronics and design. Proposals for invited talks, embedded tutorials, and panels should be sent by email to the ISLPED’26 Technical Program Co-Chairs by the deadline listed on the left. Participants interested in exhibiting at the Symposium should contact the General Chairs by May 1, 2026.